/********************************************************************************/
/** NVM: Interrupts in RAM                                                     **/
/********************************************************************************/
/** In the chip, the Flash memory is single-port: during any operation         **/
/** (read/write/erase), no other operation is possible. While an NVM           **/
/** write/erase is ongoing, any interrupt (read operation) will be held until  **/
/** NVM is ready. The execution of the ISR will be postponed for the remaining **/
/** time of the NVM operation -> ISR will be delayed.                          **/
/** To have the interrupts still executed during a Flash operation, the        **/
/** solution consists in locating the interrupt vector table + the complete    **/
/** interrupt service routines in the RAM.                                     **/
/********************************************************************************/